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LFENCE;AESDEC XMM0,XMM1;ADOX RAX,RBX on Coffee Lake 𓆡 (more architectures)

AssemblyLFENCE;AESDEC XMM0,XMM1;ADOX RAX,RBX
Architecture CodenameCoffee Lake
Port Eligibility Instr. 1None
Port Eligibility Instr. 21*p0
Port Eligibility Instr. 31*p06
Total Instr. Length (bytes)14
Cutoff 1None (348 other commands with the same cutoff)
Cutoff 2None
Graph (open in new window) (raw data)
Instruction 1LFENCE
Swap 🔄 Instruction 2 AESDEC XMM0,XMM1 (60 other commands with the same Instruction 2)
Instruction 3ADOX RAX,RBX (60 other commands with the same Instruction 3)
Number of instructions3
Graph Generationpython3 unroll_csv.py -a CFL -asm "LFENCE;AESDEC XMM0,XMM1;ADOX RAX,RBX" && python3 normalize_cycles.py
Length Instruction 1 (bytes)3
Length Instruction 2 (bytes)5
Length Instruction 3 (bytes)6
Regioningfalse
Region CharacterizationType3 𓆡 (20 other commands with the same type)
Element Order Changes Regioning Effecttrue
Element Order Change DescriptionDifferent pattern of Type17

See this command on additional architectures:

Other commands where Cutoff 1 = None:

Other commands where Instruction 2 = AESDEC XMM0,XMM1:

Other commands where Instruction 3 = ADOX RAX,RBX:

Other commands where Region Characterization = Type3: