| Assembly | LFENCE;AESDEC XMM0,XMM1;OR RAX,RBX | |
|---|---|---|
| Architecture Codename | Coffee Lake | |
| Port Eligibility Instr. 1 | None | |
| Port Eligibility Instr. 2 | 1*p0 | |
| Port Eligibility Instr. 3 | 1*p0156 | |
| Total Instr. Length (bytes) | 11 | |
| Cutoff 1 | 1061 (45 other commands with the same cutoff) | |
| Cutoff 2 | 2210 | |
| Graph (open in new window) (raw data) | ||
| Instruction 1 | LFENCE | |
| Swap 🔄 | Instruction 2 | AESDEC XMM0,XMM1 (60 other commands with the same Instruction 2) |
| Instruction 3 | OR RAX,RBX (60 other commands with the same Instruction 3) | |
| Number of instructions | 3 | |
| Graph Generation | python3 unroll_csv.py -a CFL -asm "LFENCE;AESDEC XMM0,XMM1;OR RAX,RBX" && python3 normalize_cycles.py | |
| Length Instruction 1 (bytes) | 3 | |
| Length Instruction 2 (bytes) | 5 | |
| Length Instruction 3 (bytes) | 3 | |
| Regioning | true | |
| Region Characterization | Type5 𓀡 (97 other commands with the same type) | |
| Element Order Changes Regioning Effect | true | |
| Element Order Change Description | Different pattern of Type24 | |