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LFENCE;AESENC XMM0,XMM1;XOR RAX,RBX on Coffee Lake (more architectures)

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AssemblyLFENCE;AESENC XMM0,XMM1;XOR RAX,RBX
Architecture CodenameCoffee Lake
Port Eligibility Instr. 1None
Port Eligibility Instr. 21*p0 (696 other cmds. with the same port eligibility for instr. 2)
Port Eligibility Instr. 31*p0156 (6662 other cmds. with the same port eligibility for instr. 3)
(228 other cmds. with the same port eligibility for both instr. 2 and instr. 3)
Total Instr. Length (bytes)11
Cutoff 11204 (174 other commands with the same cutoff)
Cutoff 22408
Instruction 1LFENCE
Swap 🔄 Instruction 2 AESENC XMM0,XMM1 (444 other commands with the same Instruction 2)
Instruction 3XOR RAX,RBX (444 other commands with the same Instruction 3)
Number of instructions3
Graph Generationpython3 unroll_csv.py -a CFL -asm "LFENCE;AESENC XMM0,XMM1;XOR RAX,RBX" && python3 normalize_cycles.py
Length Instruction 1 (bytes)3
Length Instruction 2 (bytes)5
Length Instruction 3 (bytes)3
Regioningtrue
Region Characterization Type16 (298 other commands with the same type)
Element Order Changes Regioning Effecttrue
Element Order Change DescriptionDifferent pattern of Type27

LFENCE;AESENC XMM0,XMM1;XOR RAX,RBX on additional architectures:

Other commands where Cutoff 1 = 1204:

174 instructions, click for details

Other commands where Instruction 2 = AESENC XMM0,XMM1:

444 instructions, click for details

Other commands where Instruction 3 = XOR RAX,RBX:

444 instructions, click for details

Other commands where Region Characterization = Type16:

298 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p0:

696 instructions, click for details

Other commands where the port eligibility for Instruction 3 is 1*p0156:

6662 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p0 and for Instruction 3 is 1*p0156: