uops-again.info

LFENCE;BLSI RAX,RBX;CBW on Cascade Lake (more architectures)

(open in new window) (raw data)
AssemblyLFENCE;BLSI RAX,RBX;CBW
Architecture CodenameCascade Lake
Port Eligibility Instr. 1None
Port Eligibility Instr. 21*p15 (1576 other cmds. with the same port eligibility for instr. 2)
Port Eligibility Instr. 31*p0156 (6662 other cmds. with the same port eligibility for instr. 3)
(496 other cmds. with the same port eligibility for both instr. 2 and instr. 3)
Total Instr. Length (bytes)10
Cutoff 11418 (45 other commands with the same cutoff)
Cutoff 22834
Instruction 1LFENCE
Swap 🔄 Instruction 2 BLSI RAX,RBX (398 other commands with the same Instruction 2)
Instruction 3CBW (445 other commands with the same Instruction 3)
Number of instructions3
Graph Generationpython3 unroll_csv.py -a CSL -asm "LFENCE;BLSI RAX,RBX;CBW" && python3 normalize_cycles.py
Length Instruction 1 (bytes)3
Length Instruction 2 (bytes)5
Length Instruction 3 (bytes)2
Regioningtrue
Region Characterization Type17 (568 other commands with the same type)
Element Order Changes Regioning Effecttrue
Element Order Change DescriptionDifferent pattern of Type47

LFENCE;BLSI RAX,RBX;CBW on additional architectures:

Other commands where Cutoff 1 = 1418:

45 instructions, click for details

Other commands where Instruction 2 = BLSI RAX,RBX:

398 instructions, click for details

Other commands where Instruction 3 = CBW:

445 instructions, click for details

Other commands where Region Characterization = Type17:

568 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p15:

1576 instructions, click for details

Other commands where the port eligibility for Instruction 3 is 1*p0156:

6662 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p15 and for Instruction 3 is 1*p0156: