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LFENCE;VMOVHLPS XMM0,XMM1,XMM2;ADC RAX,RBX on Cascade Lake (more architectures)

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AssemblyLFENCE;VMOVHLPS XMM0,XMM1,XMM2;ADC RAX,RBX
Architecture CodenameCascade Lake
Port Eligibility Instr. 1None
Port Eligibility Instr. 21*p5 (2846 other cmds. with the same port eligibility for instr. 2)
Port Eligibility Instr. 31*p06 (1248 other cmds. with the same port eligibility for instr. 3)
(135 other cmds. with the same port eligibility for both instr. 2 and instr. 3)
Total Instr. Length (bytes)10
Cutoff 11417 (1499 other commands with the same cutoff)
Cutoff 22834
Instruction 1LFENCE
Swap 🔄 Instruction 2 VMOVHLPS XMM0,XMM1,XMM2 (444 other commands with the same Instruction 2)
Instruction 3ADC RAX,RBX (444 other commands with the same Instruction 3)
Number of instructions3
Graph Generationpython3 unroll_csv.py -a CSL -asm "LFENCE;VMOVHLPS XMM0,XMM1,XMM2;ADC RAX,RBX" && python3 normalize_cycles.py
Length Instruction 1 (bytes)3
Length Instruction 2 (bytes)4
Length Instruction 3 (bytes)3
Regioningtrue
Region Characterization Type52 (127 other commands with the same type)
Element Order Changes Regioning Effecttrue
Element Order Change DescriptionDifferent pattern of Type35

LFENCE;VMOVHLPS XMM0,XMM1,XMM2;ADC RAX,RBX on additional architectures:

Other commands where Cutoff 1 = 1417:

1499 instructions, click for details

Other commands where Instruction 2 = VMOVHLPS XMM0,XMM1,XMM2:

444 instructions, click for details

Other commands where Instruction 3 = ADC RAX,RBX:

444 instructions, click for details

Other commands where Region Characterization = Type52:

127 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p5:

2846 instructions, click for details

Other commands where the port eligibility for Instruction 3 is 1*p06:

1248 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p5 and for Instruction 3 is 1*p06: