| Assembly | LFENCE;BLSI RAX,RBX;MULPS XMM0,XMM1 | |
|---|---|---|
| Architecture Codename | Skylake | |
| Port Eligibility Instr. 1 | None | |
| Port Eligibility Instr. 2 | 1*p15 (1576 other cmds. with the same port eligibility for instr. 2) | |
| Port Eligibility Instr. 3 | 1*p01 (1344 other cmds. with the same port eligibility for instr. 3) | |
| (80 other cmds. with the same port eligibility for both instr. 2 and instr. 3) | ||
| Total Instr. Length (bytes) | 11 | |
| Cutoff 1 | None (10976 other commands with the same cutoff) | |
| Cutoff 2 | None | |
| Instruction 1 | LFENCE | |
| Swap 🔄 | Instruction 2 | BLSI RAX,RBX (398 other commands with the same Instruction 2) |
| Instruction 3 | MULPS XMM0,XMM1 (444 other commands with the same Instruction 3) | |
| Number of instructions | 3 | |
| Graph Generation | python3 unroll_csv.py -a SKL -asm "LFENCE;BLSI RAX,RBX;MULPS XMM0,XMM1" && python3 normalize_cycles.py | |
| Length Instruction 1 (bytes) | 3 | |
| Length Instruction 2 (bytes) | 5 | |
| Length Instruction 3 (bytes) | 3 | |
| Regioning | true | |
| Region Characterization | Type51 (828 other commands with the same type) | |
| Element Order Changes Regioning Effect | true | |
| Element Order Change Description | Different pattern of Type6 | |