| Assembly | LFENCE;IMUL RAX,RBX;ADCX RAX,RBX | |
|---|---|---|
| Architecture Codename | Skylake | |
| Port Eligibility Instr. 1 | None | |
| Port Eligibility Instr. 2 | 1*p1 (2358 other cmds. with the same port eligibility for instr. 2) | |
| Port Eligibility Instr. 3 | 1*p06 (1248 other cmds. with the same port eligibility for instr. 3) | |
| (115 other cmds. with the same port eligibility for both instr. 2 and instr. 3) | ||
| Total Instr. Length (bytes) | 13 | |
| Cutoff 1 | None (10976 other commands with the same cutoff) | |
| Cutoff 2 | None | |
| Instruction 1 | LFENCE | |
| Swap 🔄 | Instruction 2 | IMUL RAX,RBX (444 other commands with the same Instruction 2) |
| Instruction 3 | ADCX RAX,RBX (350 other commands with the same Instruction 3) | |
| Number of instructions | 3 | |
| Graph Generation | python3 unroll_csv.py -a SKL -asm "LFENCE;IMUL RAX,RBX;ADCX RAX,RBX" && python3 normalize_cycles.py | |
| Length Instruction 1 (bytes) | 3 | |
| Length Instruction 2 (bytes) | 4 | |
| Length Instruction 3 (bytes) | 6 | |
| Regioning | true | |
| Region Characterization | Type20 (326 other commands with the same type) | |
| Element Order Changes Regioning Effect | true | |
| Element Order Change Description | Different pattern of Type17 | |