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LFENCE;STC;ADOX RAX,RBX on Skylake (more architectures)

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AssemblyLFENCE;STC;ADOX RAX,RBX
Architecture CodenameSkylake
Port Eligibility Instr. 1None
Port Eligibility Instr. 21*p0156 (6662 other cmds. with the same port eligibility for instr. 2)
Port Eligibility Instr. 31*p06 (1248 other cmds. with the same port eligibility for instr. 3)
(479 other cmds. with the same port eligibility for both instr. 2 and instr. 3)
Total Instr. Length (bytes)10
Cutoff 11212 (463 other commands with the same cutoff)
Cutoff 22424
Instruction 1LFENCE
Swap 🔄 Instruction 2 STC (444 other commands with the same Instruction 2)
Instruction 3ADOX RAX,RBX (350 other commands with the same Instruction 3)
Number of instructions3
Graph Generationpython3 unroll_csv.py -a SKL -asm "LFENCE;STC;ADOX RAX,RBX" && python3 normalize_cycles.py
Length Instruction 1 (bytes)3
Length Instruction 2 (bytes)1
Length Instruction 3 (bytes)6
Regioningtrue
Region Characterization Type0 (642 other commands with the same type)
Element Order Changes Regioning Effectfalse
Element Order Change DescriptionSame Pattern

LFENCE;STC;ADOX RAX,RBX on additional architectures:

Other commands where Cutoff 1 = 1212:

463 instructions, click for details

Other commands where Instruction 2 = STC:

444 instructions, click for details

Other commands where Instruction 3 = ADOX RAX,RBX:

350 instructions, click for details

Other commands where Region Characterization = Type0:

642 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p0156:

6662 instructions, click for details

Other commands where the port eligibility for Instruction 3 is 1*p06:

1248 instructions, click for details

Other commands where the port eligibility for Instruction 2 is 1*p0156 and for Instruction 3 is 1*p06: